A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm

Author:

Seo Young-Ho,Kim Dong-Wook

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Cited by 32 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

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2. Power Effective Multiply Accumulation Configuration For Low Power Applications Using Modified Parallel Prefix Adders;2023 International Conference on Applied Intelligence and Sustainable Computing (ICAISC);2023-06-16

3. FPGA Implementation of a Resource Efficient Vedic Multiplier using SPST Adders;Engineering, Technology & Applied Science Research;2023-06-02

4. Analysis of Low-Delay in 64-bit Vedic multiplier based MAC unit;2023 International Conference for Advancement in Technology (ICONAT);2023-01-24

5. A reconfigurable high-speed and low-complexity residue number system-based multiply-accumulate channel filter for software radio receivers;World Journal of Engineering;2022-08-18

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