Cellular Automata Based Test Design for Coherence Verification in 3D Caches

Abstract

To provide high vertical interconnection density between device tiers, Through Silicon Via (TSV) offers a promising solution in 3D caches. It reduces the length of global interconnection and ensures high speed cache memory access. Maintaining coherency of shared data in such caches is, however, very crucial and, therefore, demands that the reliability and accuracy of TSVs as well as the cache coherence controller (CC) are to be ensured. In the current work, we propose an elegant test solution for at-speed detection of stuck-at-faults in TSVs (offline test) as well as verification for the functioning of CC (online test). The proposed test structure is designed around the modular and cascadable structure of Cellular Automata (CA) to achieve a cost-effective realization of test and coherence verification in 3D caches with high degree of scalability. It ensures correct decisions in more than 71% cases even if the test hardware is subjected to single stuck-at-fault.