Efficient Realization of Fixed-Point Binary and Ternary Adders on FPGAs

Abstract

Binary and ternary adders are frequently used to speed-up many digital signal processing (DSP) operations like multiplication, compression, filtering, convolution, etc. FPGA realization of these circuits uses a combination of look-up tables (LUTs) and carry-chains. Alternatively, inbuilt operators and parameterizable IP cores provide an efficient means of implementing these circuits. However, the realization is not optimal in the sense that the full potential of the underlying resources is not utilized. In this paper, we use technology-dependent approaches to restructure the Boolean networks corresponding to these circuits. The restructured networks are then mapped optimally onto the FPGA fabric using minimum possible resources. Our analysis shows a subsequent speed-up in the performance of these circuits when compared to different conventional and existing approaches.