A High Bandwidth (DC-40 GHz) Pseudo Differential Distributed Amplifier in 0.18-μm RF CMOS

Abstract

This study presents a CMOS distributed amplifier (DA) with pseudo differential amplifying that achieves DC-40[Formula: see text]GHz bandwidth (BW) in 0.18-[Formula: see text]m RF CMOS process. The DA with three-stage amplifying cells was proposed to improve the DA performance. The inter-stage was composed of pseudo differential amplifying for bandwidth extension. By incorporating the pseudo differential amplifier configuration and capacitor-less circuit in the stages, the DA provides average gain and high bandwidth. The simulation results showed that the DA has a S[Formula: see text] of 6.4[Formula: see text]dB, 3-dB BW from DC up to 40[Formula: see text]GHz. It also has a minimum noise figure (NF) of 4.27[Formula: see text]dB, one dB compression point (P[Formula: see text] of [Formula: see text]3.5[Formula: see text]dBm, a high reverse isolation S[Formula: see text] of less than [Formula: see text]15[Formula: see text]dB, an input return loss S[Formula: see text] and output return loss S[Formula: see text] of less than [Formula: see text]16 and [Formula: see text]12[Formula: see text]dB, respectively. It consumes 115[Formula: see text]mW and occupies a total active area of 0.27[Formula: see text]mm2.