NOVEL TEST GENERATION ALGORITHM FOR COMBINATION CIRCUITS

Abstract

It has been known for many years that combinational circuits have a Complete Test Set (CTS) which is capable of detecting all single and multiple faults. In this paper, we attempt to find CTS systematically. Our algorithm finds a test set which detects all single and multiple stuck-at faults in combinational circuits. This test set is obtained without probing internal nodes, using fault simulation or fault enumeration. It is shown that the test set is independent of logic circuit structure and dependent to the mapping function, number of inputs, outputs, and fanout stems. An upper-bound and lower-bound figures for the number of test vectors required to obtain 100% fault coverage are provided. This number is a small fraction of the entire solution space. A number of recommendations are made to improve the testability of a logic circuit.