A Statistical Test Generation Based on Mutation Analysis for Improving the Hardware Trojan Detection

Abstract

Hardware Trojan has become a major threat to the security and trustworthiness of integrated circuit (IC) employed in critical applications. Due to the presence of process variations and measurement noises, all existing side-channel Trojan detection approaches suffer from low detection sensitivity or even false negatives with increasing circuit size and decreasing Trojan size. In this paper, we propose a statistical test generation approach based on mutation analysis, which generates a set of test vectors aiming at activating the hardware Trojan inserted into the low activity nodes. Such approach not only enhances the controllability of low activity nodes through increasing the switching activity of it, but also improves the observability by propagating the artificial designed errors introduced by the mutant to the outputs. Simulation results of a set of ISCAS’85 and ISCAS’89 benchmark circuits show that the proposed approach improves the activity of low activity nodes 463% at most compared with the Multiple Excitation of Rare Occurrence (MERO) approach and increases the Trojan coverage with 84.08% reduction in test length. Moreover, the test vectors generated by the proposed approach and the MERO approach, respectively, are exerted to the circuit under test. Experimental results demonstrate that the Mahalanobis distance margin of the proposed approach is much greater than the MERO approach, and thus provide a comparable robustness with decreasing Trojan size.