COMPLEX CMOS GATE COLLAPSING TECHNIQUE AND ITS APPLICATION TO TRANSIENT TIME

Abstract

In this paper we present a technique to collapse a CMOS gate into an equivalent inverter. This technique considers deep submicron effects such as mobility degradation and velocity saturation as well as operation regions of both the NMOS and PMOS networks of the considered CMOS gate. In addition, the model accounts for the effect of the gate's internodal capacitances on the behavior of the equivalent Series Connected MOSFET Structure. Depending on the CMOS inverter transition time model presented in Ref. 1, the developed model has accurately predicted the transition time of different CMOS gates. Considering various loads, input switching, and transistor sizes, the model shows an average error of 6%, including the error introduced by the inverter model, as compared to BSIM3v3 using Spectre.