Design and Implementation of Multiplierless FIR Filter Using COOT Bird Optimization Algorithm with Different Architectures*

Abstract

FIR filter design and implementation are the requirements of most DSP systems. The design objective of the FIR filter is nondifferentiable, nonlinear and multimodal in nature. Therefore, FIR filter design through optimization methods is most frequently employed. In the proposed work, COOT bird optimization-based FIR filters are designed. The FIR filters based on particle swarm optimization (PSO) and flower pollination optimization (FPA) algorithms are also designed for comparison. The objective function based on mean square error minimization is formulated. The low-pass, high-pass, band-pass and band-stop FIR filters of different order are designed to show the efficacy of the proposed method. COOT provides minimum passband and stopband ripples, fast convergence and less execution time for all the designed filters. The proposed technique is also compared with the existing approaches and provides a reduction in passband ripples, stopband ripples and stopband attenuation. To reduce the complexity of FIR filters, multiplierless techniques canonical signed digit (CSD), factorized canonical signed digit (FCSD) and distributed arithmetic (DA) are utilized for the implementation of FIR filters on Basys-3 (Artix-7) FPGA Board. The multiplier-based architecture is also implemented for comparison. Hardware resource utilization and dynamic power consumption of each architecture are compared. DA showed 92.16, 89.96 and 90.11% reduction in the number of LUTs, and 91.16, 89.68 and 89.77% reduction in dynamic power consumption from the multiplier, CSD and FCSD-based architectures, respectively.