Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization-Reference-Cited by-同舟云学术

Efficient FPGA based architecture for high‐order FIR filtering using simultaneous DSP and LUT reduced utilization

Author:

Maamoun Mountassar¹²,Hassani Adnane²,Dahmani Samir¹,Ait Saadi Hocine¹,Zerari Ghania¹,Chabini Noureddine³,Beguenane Rachid³

Affiliation:

1. LATSI Laboratory Department of Electronics University of Blida Blida Algeria

2. LSIC Laboratory Department of Physics ENS de Kouba Vieux‐Kouba Algiers Algeria

3. Department of Electrical and Computer Engineering Royal Military College of Canada Kingston Canada

Publisher

Institution of Engineering and Technology (IET)

Subject

Electrical and Electronic Engineering,Control and Systems Engineering

Link

Reference34 articles.

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

2. A FPGA implementation of Resonance Demodulation and its Spectrum Analysis;2023 2nd International Conference on Computing, Communication, Perception and Quantum Technology (CCPQT);2023-08-04

3. Low Area Implementation of FIR Filter Based on FPGA Using Approximation Method;2023 3rd International Scientific Conference of Engineering Sciences (ISCES);2023-05-03

4. Hardware Acceleration of FIR Filter Implementation on ZYNQ SoC;2022 IEEE 16th International Conference on Application of Information and Communication Technologies (AICT);2022-10-12