A 5-mW, 1.2–3.5-GHz Capacitive Degeneration in LC-Digitally-Controlled Oscillator for Nano-Satellite Frequency Synthesizers in 90-nm CMOS
Author:
Affiliation:
1. Microelectronic and Instrumentation Laboratory (LR-13ES12), Faculty of Sciences, University of Monastir, 5019 Monastir, Tunisia
2. Research Center for Microelectronics and Nanotechnology (CRMN), Techno-park of Sousse, 4000 Sousse, Tunisia
Abstract
Publisher
World Scientific Pub Co Pte Lt
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture
Link
https://www.worldscientific.com/doi/pdf/10.1142/S0218126616501590
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1. An all-digital PLL for frequency multiplication by 4 to 1022 with seven-cycle lock time
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