Efficient FTL-Aware Data Categorization and Identification Scheme for Flash Memory

Author:

Ayele Sololia Gudeta1,Jin Rize1,Kwon Se Jin1,Attique Muhammad1,Chung Tae-Sung1

Affiliation:

1. Department of Computer Engineering, Ajou University San 5, Woncheon-Dong, Yeongtong-Gu, Suwon 443–749, South Korea

Abstract

Hot data identification in flash memory is of great interest because it significantly affects the garbage collection and wear-leveling performance. Presently, certain hot and cold data classification schemes based on Bloom filters (BFs) have been proposed. Although BFs are efficient in most cases, there is a significant trade-off between false positive rates, which are the result of hash value collisions and memory utilization. In this paper, we suggest a better data categorization mechanism that is based on a hashing technique called Fingerprinting by Random Polynomials with the aim of reducing false positive rates and achieving lower memory consumption compared to the BF-based schemes. We also introduce a new methodology for classifying write requests by linking the definition of hot and cold write requests to the flash memory software layer, the flash translation layer (FTL) characteristics. Our approach improves space utilization by representing each logical block number (lbn) by one counter in the hash table, and achieves an extremely low error rate by choosing the degree of the hash function based on the address space of the flash memory. In addition, we achieved lower false identification rates. We demonstrate the performance using mathematical analysis and trace-driven simulation.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Managing Massive Amounts of Small Files in All-Flash Storage;2020 IEEE 44th Annual Computers, Software, and Applications Conference (COMPSAC);2020-07

2. A Group-Based Buffer Management for SSD;Journal of Circuits, Systems and Computers;2019-11

3. Hierarchical Request-Size-Aware Flash Translation Layer Based on Page-Level Mapping;Journal of Circuits, Systems and Computers;2019-06-27

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