A Method of Fast Evaluation of an MC Placement for Network-on-Chip

Abstract

On-chip Memory-Controllers (MCs) placement is a key issue in designing Network-on-Chip (NoC) with multiple MCs. A good MC placement can efficiently decrease NoC memory-access latency. However, it is difficult to search an optimal MC placement within a feasible time period due to huge design space of MC placements and much time spent on evaluating whether an MC placement is better or not. This paper focuses on how to evaluate an MC placement quickly. As a common manner of evaluating an MC placement, network simulation manners often cost too much time. In this paper, we propose a method of fast evaluation of an MC placement. There are two contributions in this paper: the first one is to use an indicator “path-load” to approximately represent memory-access-flow transmission latency; the second one is to propose a highly-efficient method of calculating path-load to evaluate an MC placement to take the place of traditional simulation manner. To verify this method, we embed it into a traversal method to find out optimal MCs placements. Experiments show that almost all MCs placements with the minimum path load value are those placements that are of the best network performance in the same network scenarios. In a word, our proposed method can efficiently evaluate MCs placements rather than simulation manners. It can be embedded into searching algorithm to accelerate achieving optimal solutions.