FPGA Implementation of Wavelet Neural Network Training with PSO/iPSO

Abstract

In this study, field-programmable gate array (FPGA)-based hardware implementation of the wavelet neural network (WNN) training using particle swarm optimization (PSO) and improved particle swarm optimization (iPSO) algorithms are presented. The WNN architecture and wavelet activation function approach that is proper for the hardware implementation are suggested in the study. Using the suggested architecture and training algorithms, test operations are implemented on two different dynamic system recognition problems. From the test results obtained, it is observed that WNN architecture generalizes well and the activation function suggested has approximately the same success rate with the wavelet function defined in the literature. In the FPGA-based implementation, IEEE 754 floating-point number format is used. Experimental tests are done on Xilinx Artix 7 xc7a100t-1csg324 using ISE Webpack 14.7 program.