ELECTRICAL CHARACTERIZATION OF PLANAR SILICON NANOWIRE FIELD-EFFECT TRANSISTORS

Abstract

Silicon nanowires (Si NWs) are promising candidates for field-effect transistor (FET) conduction channel. Planar configuration using a back gate is an easy way to study these devices. We demonstrate the possibility to build high performance FET using a simple silicidation process leading to high effective holes' mobility between 130 cm2⋅V-1⋅s-1 and 200 cm2⋅V-1⋅s-1 and good ION/IOFF ratio up to 105. Moreover we investigated the possibility to passivate the NWs using either a high-k dielectric layer or a thermal oxide shell around the NWs. This leads to a reduction of the hysteretic behavior during the gate voltage sweep from 30 V to 1 V depending on the material and the gate configuration.