THERMOMECHANICAL MODELING OF ELECTRONIC PACKAGES

Abstract

This paper is concerned with an integrated thermomechanical modeling and analysis of electronic packages. As the technology advances in terms of speed and density of circuit within a chip, the power dissipation increases exponentially. The packages are subjected to heating during fabrication, testing, and service. Due to the heterogeneous construction with wide mismatch of material properties, thermal stresses are induced which would result in mechanical failures such as cracking and delamination. It is essential to analyze the packages for thermal and stress fields and check their compliance with the design requirements. Earlier investigations were mostly based on approximate models such as plane-stress, plane-strain, and axisymmetric conditions. In reality, none of the packages satisfies the conditions associated with these models. In this work, 3D solid finite element with variable nodes, 8–21 nodes per element is employed. Software has been developed with the following features: sequentially coupled thermomechanical modeling, nonlinear transient solution capability, incompatible mode option when 8-node brick element is used, better estimation of nodal stresses by transformation from gauss point stresses, and quadratic criterion for delamination failure. A flipchip has been analyzed using the software developed for their thermal and stress fields. Numerical results indicate: the junction temperatures exceed the specification limits for higher heat dissipation, if appropriate cooling is not applied. The stresses in the die corner and at the solder balls are critical. Three-dimensional modeling is necessary for estimation of the same. Appropriate failure criterion was used in the failure prediction.