Design Exploration of mm-Wave Integrated Transceivers for Short-Range Mobile Communications Towards 5G

Abstract

This paper presents a design exploration, at both system and circuit levels, of integrated transceivers for the upcoming fifth generation (5G) of wireless communications. First, a system level model for 5G communications is carried out to derive transceiver design specifications. Being 5G still in pre-standardization phase, a few currently used standards (ECMA-387, IEEE 802.15.3c, and LTE-A) are taken into account as the reference for the signal format. Following a top-down flow, this work presents the design in 65[Formula: see text]nm CMOS SOI and bulk technologies of the key blocks of a fully integrated transceiver: low noise amplifier (LNA), power amplifier (PA) and on-chip antenna. Different circuit topologies are presented and compared allowing for different trade-offs between gain, power consumption, noise figure, output power, linearity, integration cost and link performance. The best configuration of antenna and LNA co-design results in a peak gain higher than 27[Formula: see text]dB, a noise figure below 5[Formula: see text]dB and a power consumption of 35[Formula: see text]mW. A linear PA design is presented to face the high Peak to Average Power Ratio (PAPR) of multi-carrier transmissions envisaged for 5G, featuring a 1[Formula: see text]dB compression point output power (OP1dB) of 8.2[Formula: see text]dBm. The delivered output power in the linear region can be increased up to 13.2[Formula: see text]dBm by combining four basic PA blocks through a Wilkinson power combiner/divider circuit. The proposed circuits are shown to enable future 5G connections, operating in a mm-wave spectrum range (spanning 9[Formula: see text]GHz, from 57[Formula: see text]GHz to 66[Formula: see text]GHz), with a data-rate of several Gb/s in a short-range scenario, spanning from few centimeters to tens of meters.