HARDWARE REDUCTION IN FPGA-BASED MOORE FSM-Reference-Cited by-同舟云学术

HARDWARE REDUCTION IN FPGA-BASED MOORE FSM

Published:2013-03 Issue:03 Volume:22 Page:1350006
ISSN:0218-1266
Container-title:Journal of Circuits, Systems and Computers
language:en
Short-container-title:J CIRCUIT SYST COMP

Author:

BARKALOV ALEXANDER¹,TITARENKO LARYSA¹,MALCHEVA RAISA²,SOLDATOV KYRYLL²

Affiliation:

1. Institute of Informatics and Electronics, University of Zielona Gora, Licealna Str., 9, Zielona Gora, 65-417, Poland

2. Donetsk National Technical University, Artema Str., 58, Donetsk, 83-001, Ukraine

Abstract

The methods are proposed targeting to reduce the numbers of both look-up table elements and embedded memory blocks in the logic circuit of a Moore finite state machine. The proposed methods are based on binary encoding of both classes of pseudoequivalent states and collections of microoperations. Examples of synthesis and results of investigations are given.

Publisher

World Scientific Pub Co Pte Lt

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture

Link

https://www.worldscientific.com/doi/pdf/10.1142/S0218126613500060

Reference30 articles.

1. Logic Synthesis for Control Automata

2. Logic Synthesis for FSM-Based Control Units

3. Synthesis of finite state machines for CPLDs

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