A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC

Abstract

A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.