Design of Low Leakage Variability Aware ONOFIC CMOS Standard Cell Library

Abstract

In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and buffer logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8[Formula: see text]V by using Silvaco’s EDA tools. All generated cells have same cell height of 1.58 [Formula: see text]m. The proposed logic cells attain large leakage and power delay product (PDP) reduction. ISCAS’85 benchmark circuits 74181 and c17 are designed and verified with developed logic cells at transistor level. The ONOFIC standard cell library reduces 34.40% and 42.74% leakage power and improves PDP by 18.34% and 16.46% for 74181 and c17 circuits, respectively. The result of generated standard cell library shows that it is a good choice for low leakage applications.