Affiliation:
1. National ASIC System Engineering Research Center, Southeast University, Sipailou, No. 2, Nanjing, Jiangsu Province 210096, P. R. China
Abstract
Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADCs recently are reported and several noteworthy trends can be observed from the statistical results.
Funder
The Fundamental Research Funds for the Central Universities
Publisher
World Scientific Pub Co Pte Lt
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Electrical and Electronic Engineering,Hardware and Architecture
Cited by
13 articles.
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