Parasitic extraction and power loss estimation of power devices

Abstract

Abstract This study aims to characterize the switching transients and power losses of silicon (Si) power metal–oxide–semiconductor field-effect transistor (MOSFET) in an SOT-227 package (hereinafter named “power MOSFET package”) and Si power MOSFET-based three-phase MOSFET inverter during load cycles through numerical modeling and experimental validation. The three-phase inverter comprises six power MOSFET packages as switches for brushless direct current motor drive. First of all, three-dimensional electromagnetic analyses are performed to extract the parasitic parameters of these two power devices. Subsequently, the device model and the previously derived package model of the power MOSFET are combined together in circuit simulation of a double pulse test (DPT). The calculated waveform profiles and switching times are compared with those obtained from the DPT experiment. Likewise, an effective compact circuit simulation model of the three-phase six-switch inverter, considering the parasitic effects, is developed for the switching loss estimation in the first switching interval of the six-step switching sequence. At last, parametric study is performed to explore, respectively, the influences of some crucial factors on the parasitic inductances and switching transients of the power MOSFET package and the switching losses of the three-phase inverter.