Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver-Reference-Cited by-同舟云学术

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Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver

Published:2007-06-01 Issue:6 Volume:E90-C Page:1274-1281
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Transactions on Electronics

Author:

KUBOKI T.,TSUCHIYA A.,ONODERA H.

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Perspective Chapter: Chip I/O Design Fundamentals, Methodologies and Challenges;Industrial Engineering and Management;2024-07-31

2. A power-efficient switchable CML driver at 10 Gbps;Journal of Semiconductors;2016-02

3. 10 Gbps Current Mode Logic I/O Buffer;Communications in Computer and Information Science;2013

4. A 14-GHz AC-Coupled Clock Distribution Scheme With Phase Averaging Technique Using Single LC-VCO and Distributed Phase Interpolators;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2011-11

5. Dual-Level LVDS Technique for Reducing Data Transmission Lines by Half in LCD Driver IC's;IEICE Transactions on Electronics;2008-01-01

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