Logic and Analog Test Schemes for a Single-Chip Pixel-Parallel Fingerprint Identification LSI
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Published:2007-10-01
Issue:10
Volume:E90-C
Page:1892-1899
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ISSN:0916-8524
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Container-title:IEICE Transactions on Electronics
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language:en
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Short-container-title:IEICE Transactions on Electronics
Author:
SHIGEMATSU S.,MORIMURA H.,SHIMAMURA T.,HATANO T.,IKEDA N.,OKAZAKI Y.,MACHIDA K.,NAKANISHI M.
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Cited by
1 articles.
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