Physical design challenges to nano-CMOS circuits
Author:
Affiliation:
1. Integrated Research Institute, Tokyo Institute of Technology
2. Interdisciplinary Graduate School of Science and Engineering, Tokyo Institute of Technology
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
http://www.jstage.jst.go.jp/article/elex/6/11/6_11_703/_pdf
Reference39 articles.
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2. [2] T. Ohmi, “ULSI reliability through ultraclean processing, ”Proc. IEEE, Special Issue on VLSI Reliability, vol. 81, no. 5, pp. 716-729, May 1993.
3. Design Guidelines and Process Quality Improvement for Treatment of Device Variations in an LSI Chip
4. [4] K. Takeuchi, T. Fukai, T. Tsunomura, A. T. Putra, A. Nishida, S. Kamohara, and T. Hiramoto, “Understanding random threshold voltage fluctuation by comparing multiple fabs and technologies, ”IEEE International Electron Devices Meeting (IEDM), pp. 467-470, Dec. 2007.
5. [5] T. Sato, H. Ueyama, N. Nakayama, and K. Masu, “A MOS transistor array with pico-ampere order precision for accurate characterization of leakage current variation, ”IEEE Asian Solid-State Circuit Conference (ASSCC), pp. 389-392, Nov. 2008.
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