Timing violations due to VDD/VSS bounce-Reference-Cited by-同舟云学术

Timing violations due to VDD/VSS bounce

Published:2006-09-06 Issue: Volume:4 Page:197-205
ISSN:1684-9973
Container-title:Advances in Radio Science
language:en
Short-container-title:Adv. Radio Sci.

Author:

Eireiner M.,Henzler S.,Berthold J.,Pacha C.,Georgakos G.,Schmitt-Landsiedel D.

Abstract

Abstract. The effect of power supply noise in on-chip power grids and its implications on the path delay in digital circuits is examined. The simulation results show that IR-Drop and the resulting path delay are strongly affected by the layout of the circuit. Power grid design measures to reduce IR-Drop, as well as their area and performance implications are discussed.

Publisher

Copernicus GmbH

Link

https://ars.copernicus.org/articles/4/197/2006/ars-4-197-2006.pdf

Reference8 articles.

1. Benoit, M., Taylor, S., Overhauser, D., and Rochel, S.: Power Distribution in High-Performance Design, in: International Symposium on Low Power Electronics and Design, 1998.

2. Ernst, D., Austin, D. B T., Flautner, K., Mudge, T., and et~al: Razor: A low-power pipeline based on circuit-level timing speculation, in: Proc. 36th Ann. Int'l Symp. Microarchitecture (MICRO-36), IEEE CS Press, 7–18, 2003.

3. Henzler, S., Nirschl, T., Berthold, J., Georgakos, G., and Schmitt-Landsiedel, D.: Design and Technology of Fine-Grained Sleep Transistor Circuits in Ultra-Deep Sub-Micron CMOS Technologies, in: Proceedings of International Conference on Integrated Circuit Design and Technology, 2005.

4. http://www.itrs.net: International Roadmap for Semiconductors, Tech. rep., ITRS, 2003.

5. Lin, S. and Chang, N.: Challenges in Power-Ground Integrity., in: ICCAD, 651, 2001.

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