Sparse matrix-vector multiplication on network-on-chip
-
Published:2010-12-22
Issue:
Volume:8
Page:289-294
-
ISSN:1684-9973
-
Container-title:Advances in Radio Science
-
language:en
-
Short-container-title:Adv. Radio Sci.
Author:
Sun C.-C.,Götze J.,Jheng H.-Y.,Ruan S.-J.
Abstract
Abstract. In this paper, we present an idea for performing matrix-vector multiplication by using Network-on-Chip (NoC) architecture. In traditional IC design on-chip communications have been designed with dedicated point-to-point interconnections. Therefore, regular local data transfer is the major concept of many parallel implementations. However, when dealing with the parallel implementation of sparse matrix-vector multiplication (SMVM), which is the main step of all iterative algorithms for solving systems of linear equation, the required data transfers depend on the sparsity structure of the matrix and can be extremely irregular. Using the NoC architecture makes it possible to deal with arbitrary structure of the data transfers; i.e. with the irregular structure of the sparse matrices. So far, we have already implemented the proposed SMVM-NoC architecture with the size 4×4 and 5×5 in IEEE 754 single float point precision using FPGA.
Publisher
Copernicus GmbH
Reference15 articles.
1. Benini, L. and Micheli, G D.: Networks on Chips: A New SoC Paradigm, Computer, 35, 70–78, 2002. 2. Bertozzi, D. and Benini, L.: Xpipes: a network-on-chip architecture for gigascale systems-on-chip, Circuits and Systems Magazine, IEEE, 4, 18–31, 2004. 3. deLorimier, M. and DeHon, A.: Floating-point sparse matrix-vector multiply for FPGAs, in: FPGA '05: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, 75–85, ACM, New York, NY, USA, \\doihttp://doi.acm.org/10.1145/1046192.1046203, 2005. 4. Elkurdi, Y., Fernández, D., Souleimanov, E., Giannacopoulos, D., and Gross, W J.: FPGA architecture and implementation of sparse matrix-vector multiplication for the finite element method, Computer Physics Communications, 178, 558–570, 2008. 5. Gregg, D., Mc Sweeney, C., McElroy, C., Connor, F., McGettrick, S., Moloney, D. and Geraghty, D.: FPGA Based Sparse Matrix Vector Multiplication using Commodity DRAM Memory, in: International Conference on Field Programmable Logic and Applications, 786–791, 2007.
Cited by
4 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
|
|