A model for threshold voltage shift under negative gate bias stress in amorphous InGaZnO thin film transistors
Author:
Publisher
EDP Sciences
Subject
Condensed Matter Physics,Instrumentation,Electronic, Optical and Magnetic Materials
Link
http://www.epjap.org/10.1051/epjap/2015150375/pdf
Reference19 articles.
1. Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors
2. A new drain current model for amorphous IGZO thin film transistors
3. The Effect of the Active Layer Thickness on the Negative Bias Stress-Induced Instability in Amorphous InGaZnO Thin-Film Transistors
4. Effect of ${\rm O}_{2}$ Flow Rate During Channel Layer Deposition on Negative Gate Bias Stress-Induced $V_{\rm th}$ Shift of a-IGZO TFTs
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1. Study of ZnO/BST interface for thin-film transistor (TFT) applications;Surfaces and Interfaces;2021-04
2. A numerical model of electrical characteristics for the monolayer graphene field effect transistors;The European Physical Journal Applied Physics;2019-06
3. A drain current model for amorphous InGaZnO thin film transistors considering temperature effects;Solid-State Electronics;2018-03
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