A Low Noise CMOS Digital Output Interface Circuit-Reference-Cited by-同舟云学术

A Low Noise CMOS Digital Output Interface Circuit

Published:2014-10 Issue: Volume:1049-1050 Page:653-656
ISSN:1662-8985
Container-title:Advanced Materials Research
language:
Short-container-title:AMR

Author:

Xu Hua¹,Qiao Zhe²

Affiliation:

1. Southwest Integrated Circuit Design Co., Ltd

2. Chongqing Acoustic-Optic-Electronic Co., Ltd

Abstract

A digital CMOS output interface circuit is proposed, which lowers down the peak and lengthen the duration of the pulse of current supplied by the power supply to reduce the SSN (simultaneously-switching noise) effects. The simulation shows that the maximal SSN voltage of the proposed circuit is 331.5mV compared to 662.4mV of the traditional one.

Publisher

Trans Tech Publications, Ltd.

Subject

General Engineering

Link

https://www.scientific.net/AMR.1049-1050.653.pdf

Reference9 articles.

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