Cleaning Requirement in the Thinning Module for 3D-Stacked IC (3D-SIC) Integration-Reference-Cited by-同舟云学术

Cleaning Requirement in the Thinning Module for 3D-Stacked IC (3D-SIC) Integration

Published:2012-04 Issue: Volume:187 Page:265-268
ISSN:1662-9779
Container-title:Solid State Phenomena
language:
Short-container-title:SSP

Author:

Wostyn Kurt¹,Zhao Ming¹,Cui Hu Shan¹,Laermans Patrick¹,Jourdain Anne¹,Verbinnen Greet¹,Struyf Herbert²,de Strycker Steven²,Claes Martine³,Travaly Youssef³,Leunissen Leonardus²

Affiliation:

1. IMEC

2. IMEC Interuniversity Microelectronics Center

3. IMEC VZW

Abstract

Exposure of TSVs from the backside in 3D-SIC is a multistep process [1-. Two steps in this process flow (thinning module) are potentially a high risk for particle contamination: wafer edge trimming and wafer thinning by grinding.

Publisher

Trans Tech Publications, Ltd.

Subject

Condensed Matter Physics,General Materials Science,Atomic and Molecular Physics, and Optics

Link

https://www.scientific.net/SSP.187.265.pdf

Reference10 articles.

1. P. Garrou, C. Bower, in Handbook of 3D Integration Vol. 1, edited by Philip Garrou, Christopher Bower and Peter Ramm (Wiley, Weinheim, 2008), pp.25-44.

2. J. Knickerbocker, P. Andry, B. Dang, R. Horton, M. Interrante, C. Pater, R. Polastre, K. Sakuma, R. Sirdeskmukh, E. Sprogis, S. Sri-Jayantha, A. Stephens, A. Topol, C. Transg, B. Webb, S. Wright, IBM J. Res. & Dev. 52 (6), 553-569 (2008).

3. D. Henry, F. Jacquet, M. Neyret, X. Baillin, T. Enot, V. Lapras, C. Brunet-Manquat, j. Charbonnier, B. Aventurier, N. Sillon, Proc. 58th Electron. Comp. Technol. Conf. (2008) pp.556-562.

4. J. Van Olmen, J. Coenen, W. Dehaene, K. De Meyer, C. Huyghebaert, C., A. Jourdain, G. Katti, A. Mercha, M. Rakowski, M. Stucchi, Y. Travaly, E. Beyne, B. Swinnen, Proc. Int. Conf. 3D Syst. Int. (2009) pp.12-16.

5. T. Bearda, Y. Travaly, K. Wostyn, S. Halder, B. Swinnen, T. Mölders, I. Varghese and P. Cheng, Proc. 59th Electron. Comp. Technol. Conf., 1-4 (2009) 1513-1516.