Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs-Reference-Cited by-同舟云学术

Selective Wet Etching in Fabricating SiGe and Ge Nanowires for Gate-all-Around MOSFETs

Published:2018-08 Issue: Volume:282 Page:101-106
ISSN:1662-9779
Container-title:Solid State Phenomena
language:
Short-container-title:SSP

Author:

Liu Wen Dar¹,Lee Yi Chia¹,Sekiguchi Ryo²,Yoshida Yukifumi³,Komori Kana³,Wostyn Kurt⁴,Sebaai Farid⁴,Holsteyns Frank⁴

Affiliation:

1. Versum Materials Technology LLC

2. Versum Materials Japan

3. SCREEN Semiconductor Solutions Co., Ltd.

4. IMEC

Abstract

A selective wet etching process for fabricating SiGe and Ge nanowires for gate all around transistors is introduced in this paper. Two formulated proprietary chemical mixtures with highly selective etching properties (Si vs. SiGe and SiGe vs. Ge) can effectively dissolve the sacrificial layers with minimal damage to the interstitial nanowire materials. The Auger Electron Spectroscopy (AES) surface characterization indicates that no chemical contamination is left after the wet etching process.

Publisher

Trans Tech Publications, Ltd.

Subject

Condensed Matter Physics,General Materials Science,Atomic and Molecular Physics, and Optics

Link

https://www.scientific.net/SSP.282.101.pdf

Reference6 articles.

1. H. Mertens et al., VLSI Tech. Dig., (2016), p.158.

2. H. Mertens et al., ECS transactions, 77(5) (2017), pp.19-30.

3. L Witters et al., IEEE transactions on electron devices, Vol.64, (2017) No. 11.

4. Kurt Wostyn et al., ECS Transactions, 69 (8) (2015), pp.147-152.

5. V. Loup et al. ECS transactions, 58 (2013), pp.47-55.

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