A Promising Hardware Accelerator with PAST Adder-Reference-Cited by-同舟云学术

A Promising Hardware Accelerator with PAST Adder

Published:2021-04-27 Issue: Volume: Page:
ISSN:1662-0356
Container-title:Materials, Computer Engineering and Education Technology
language:
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Author:

Choubey Abhishek¹,Choubey Shruti Bhargava¹

Affiliation:

1. Sreenidhi Institute of Science and Technology

Abstract

Recent neural network research has demonstrated a significant benefit in machine learning compared to conventional algorithms based on handcrafted models and features. In regions such as video, speech and image recognition, the neural network is now widely adopted. But the high complexity of neural network inference in computation and storage poses great differences on its application. These networks are computer-intensive algorithms that currently require the execution of dedicated hardware. In this case, we point out the difficulty of Adders (MOAs) and their high-resource utilization in a CNN implementation of FPGA .to address these challenge a parallel self-time adder is implemented which mainly aims at minimizing the amount of transistors and estimating different factors for PASTA, i.e. field, power, delay.

Publisher

Trans Tech Publications Ltd

Link

https://www.scientific.net/AST.105.241.pdf

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