A Fast Design Space Exploration Method for Reconfigurable Architecture Based on Loop Optimization

Abstract

Using FPGA for general-purpose computation has become a hot research topic in high-performance computing technologies. However, the complexity of design and resource of FPGA make applying a common approach to solve the problem with mixed constraints impossible. Aiming at familiar loop structure of the applications, a design space exploration method based on FPGA hardware constrains is proposed according to the FPGA chip features, which combines the features of the corresponding application to perform loop optimization for reducing the demand of memory. Experimental results show that the method significantly improves the rate of data reuse, reduces the times of external memory access, achieves parallel execution of multiple pipelining, and effectively improves the performance of applications implemented on FPGA.