Verification of Faulty Mechanism for Fan-Out Wafer Level Package Using Numerical Analysis-Reference-Cited by-同舟云学术

Verification of Faulty Mechanism for Fan-Out Wafer Level Package Using Numerical Analysis

Published:2015-09 Issue: Volume:789-790 Page:609-612
ISSN:1662-7482
Container-title:Applied Mechanics and Materials
language:
Short-container-title:AMM

Author:

Yoon Hyung Seok¹,Jeon Insu¹

Affiliation:

1. Chonnam National University

Abstract

The manufactures of the ultra-thin and smaller semiconductor chip are required over the portable electric devices. The investigation of Fan-out wafer level package (FOWLP) is used widely, among the performance improvement and miniaturization technologies. In this paper, we obtained lots of crack near the passivation (PSV) and redistributed layer (RDL) region of FOWLP during the reliability evaluation of thermal cycling test (TCT). The generated stress and deformational behavior was observed through 2D finite-element analysis. The concentrated stress and deformational behavior are observed around the Solder ball edge and RDL & PSV edges. The crack was observed experimentally as well. The verification of the mechanism for crack generation and the validity of the finite-element analysis were verified by the structural analysis.

Publisher

Trans Tech Publications, Ltd.

Link

https://www.scientific.net/AMM.789-790.609.pdf

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