Digital Design of a BCD Multiplication Scheme-Reference-Cited by-同舟云学术

Digital Design of a BCD Multiplication Scheme

Published:2011-06 Issue: Volume:63-64 Page:90-93
ISSN:1662-7482
Container-title:Applied Mechanics and Materials
language:
Short-container-title:AMM

Author:

Kong Yi Nan¹

Affiliation:

1. Macquarie University

Abstract

This paper presents a new scheme for BCD multiplication. This new scheme features a completely carry-free multiplication. The parallel structure of the new algorithm is investigated. This fast architecture was derived by looking at multiplication in a fresh perspective. A carry is able to be computed without performing multiplication on any of the previous bits. The new approach is expected to have a lot of potential contributions to digital design.

Publisher

Trans Tech Publications, Ltd.

Link

https://www.scientific.net/AMM.63-64.90.pdf

Reference11 articles.

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3. Y. H Seo and D. W. Kim, A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm, IEEE Transactions on VLSI Systems, vol. 18, issue 2, p.201–208, (2010).

4. S. R. Kuang and J. P. Wang, Design of Power-Efficient Configurable Booth Multiplier, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, issue 3, p.568–580, (2010).

5. R. Baugh and B. A. Wooley, A Two's Complement Parallel Array Multiplication Algorithm, IEEE Transactions on Computers, vol. 22, p.1045–1047, (1973).

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