A Novel Charge Pumped Clock Generator for VLSI

Abstract

In this paper, a novel charge pumped clock generator is proposed, which can pump the reference cock to a level as high as double Vcc, while keeping the low level of the clock unchanged. The proposed circuit is very suitable for low voltage IC design to attain low on-resistance of MOS switch while keeping the parasitic capacitance small, which results in high speed of the circuit. The stimulated results show that the pumped clock has rising and falling time of 50ps and 67ps respectively.