IR Lock-In Thermography Analysis to Evidence Dynamic Mis-Behavior of SiC Device Prototypes

Abstract

This paper deals with the geometry of a high voltage (1200 V) vertical JFET made with 4H silicon carbide, inspired by SIT or commercial solutions like Semisouth's one (principle exposed in Fig. 1). A first layout was designed allowing an easy integration of a free-wheeling diode. Indeed with the maturity of SiC JFET fabrication process, nowadays' trend is the high integration level of a complete power electronics system. This paper will focus on the distribution of the gate potential or the source current across the device and the relation that could be done with the switching delay. The measurements start with the classical I–V static characterization from room temperature till 225°C. After packaging the best dies, the switching behavior is studied. Gate bias and temperature dependence is also investigated. In order to fully understand the conducting/blocking or switching mechanisms, some further measurements using lock-in infrared thermography (LIRT) technique was led. Thus, with this complete characterization methodology the device layout can be improved.