Self-Calibration Techniques of Pipeline ADCs Using Cyclic Configuration
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Published:2013-12
Issue:
Volume:596
Page:181-186
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ISSN:1662-9795
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Container-title:Key Engineering Materials
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language:
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Short-container-title:KEM
Author:
Tan Yohei1, Oki Daiki1, Liu Yu1, Arai Yukiko1, Nosker Zachary1, Kobayashi Haruo1, Kobayashi Osamu2, Matsuura Tatsuji1, Yang Zhi Xiang1, Katayama Atsuhiro1, Quan Li1, Li En Si1, Niitsu Kiichi1, Takai Nobukazu1
Affiliation:
1. Gunma University 2. Semiconductor Technology Academic Research Center (STARC)
Abstract
This paper proposes a digital self-calibration technique for pipelined ADC. In this technique, the pipelined ADC is composed of a series of cyclic ADCs and each stage has independent digital self-calibration. Because of this, our technique achieves higher accuracy calibration than the conventional method that calibrates by using later stages. Applying the proposed method, we simulated the pipelined ADC with MATLAB and showed that higher accuracy calibration can be achieved with a smaller number of pipeline stages.
Publisher
Trans Tech Publications, Ltd.
Subject
Mechanical Engineering,Mechanics of Materials,General Materials Science
Reference6 articles.
1. A. Verma, B. Razavi, A 10b 500MS/s 55mW CMOS ADC, IEEE International Solid-State Circuit Conference, San Francisco (Feb. 2009). 2. T. Yagi, K. Usui, T. Matsuura, S. Uemori, Y. Tan, S. Ito, H. Kobayashi, Background Calibration Algorithm for Pipelined ADC with Open-Loop Residue Amplifier Using Split ADC Scheme, IEICE Trans. on Electronics, Vol. E94-C, no. 7, pp.1233-1236. 3. T. Ogawa, T. Matsuura, H. Kobayashi, N. Takai, M. Hotta, H. San, A. Abe, K. Yagi, T. Mori, Non-binary SAR ADC with Digital Compensation for Comparator Offset Effects, IEICE Trans. Vol. J94-C, no. 3, pp.68-78 (March 2011). 4. T. Ogawa, H. Kobayashi, N. Takai, M. Hotta, H. San, T. Matsuura, A. Abe, K. Yagi, T. Mori, Non-binary SAR ADC with Digital Error Correction for Low Power Applications, , IEEE Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia (Dec. 2010). 5. M. Hotta, M. Kawakami, H. Kobayashi, H. San, N. Takai, T. Matsuura, A. Abe, K. Yagi, T. Mori, SAR ADC Architecture with Digital Error Correction, IEEJ Trans. Electrical and Electronic Engineering, vol. 5, no. 6, pp.651-659 (Nov. 2010).
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