SAR ADC Architecture with Digital Error Correction-Reference-Cited by-同舟云学术

SAR ADC Architecture with Digital Error Correction

Published:2010-10-13 Issue:6 Volume:5 Page:651-659
ISSN:1931-4973
Container-title:IEEJ Transactions on Electrical and Electronic Engineering
language:en
Short-container-title:IEEJ Trans Elec Electron Eng

Author:

Hotta Masao,Kawakami Masayuki,Kobayashi Haruo,San Hao,Takai Nobukazu,Matsuura Tatsuji,Abe Akira,Yagi Katsuyoshi,Mori Toshihiko

Publisher

Wiley

Subject

Electrical and Electronic Engineering

Reference9 articles.

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2. ISSCC Short Course. Automotive Technology and Circuits 2005.

3. Kuttner F. A 1.2V 10b 20 MS/S non-binary successive approximation ADC in 0.13µm CMOS. Technical Digest of ISSCC 2002.

4. Hesener1 M Eichler1 T Hanneberg1 A Herbison1 D Kuttner F Wenske1 H. A 14b 40 MS/s redundant SAR ADC with 480 MHz clock in 0.13µm CMOS. Technical Digest of ISSCC, San Francisco, 13.6 2007.

5. Hotta M Hayakawa A Zhao N Takahashi Y Kobayashi H. SAR ADC architecture with digital error correction. Technical Digest of Analog VLSI Workshop 2006 2006.

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