Defect Structures at the Silicon/3C-SiC Interface

Abstract

In all heteroepitaxial systems the interface between substrate and layer is a crucial point. In this work SEM and TEM studies on the interface between silicon substrate and cubic silicon carbide (3C-SiC) layers obtained by chemical vapor deposition (CVD) are presented. A clear connection between process parameters, like the design of substrate cleaning, and the heating ramp, and resulting defect structures at the substrate-layer interface could be found. Whereas the process step of etching in hot hydrogen for oxide removal is crucial for avoiding the generation of closed voids of type 2, the design of the temperature ramp up to growth temperature during carbonization influences the interface roughness. Here a fast ramp helps to obtain a flat interface.