Affiliation:
1. Beijing Microelectronics Technology Institute
Abstract
In this paper, a design for testability methodology for a multi-mode navigation baseband SoC chip was presented, merging the various DFT techniques including boundary scan, MBIST, and full scan based ATPG. Implementation the technology of pattern compression was introduced in detail. Test results showed that this strategy is feasible, and meets the requirement of engineering applications. The test coverage of this chip is 97.53%, in the condition that, almost 30-fold test pattern compression is achieved
Publisher
Trans Tech Publications, Ltd.
Reference7 articles.
1. CAI Zhikuang, HUANG Kai, HUANG Dandan, et al: Design-for-Testability and Test of Garfield Series SoC's. Microelectronics, vol. 39, No. 5, pp.593-596 (2009).
2. SUN Bo, HEI Yong, QIAO Shushan: Testability Design of Digital Television Baseband SoC Chip. Video Engineering, vol. 34, No. 7, pp.47-50 (2010).
3. N. Ahmed, C. P. Ravikumar, M. Tehranipoor and J. Plusquellic: At-Speed Transition Fault Testing With Low Speed Scan Enable. In: 23th IEEE Proceedings of VLSI Test Symposium, pp.42-47, IEEE Press, Palm Springs (2005).
4. George K, Chen C: Logic Built-In Self-Test for Core-Based Designs on System-on-a-Chip. In: IEEE Transaction on Instrumentation and Measurement, vol. 58, No. 5, pp.1495-1504, IEEE Press, (2009).
5. Zhanglei W, Chakrabarty K, Seongmoon W: Integrated LFSR Reseeding, Test Access Optimization, and Test Scheduling for Core-Based System-on-Chip. In: IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, No. 8, pp.1251-1264, IEEE Press, (2009).