Ancient Vedic Multiplication Based Optimized High Speed Arithmetic Logic

Abstract

Here, we deal with most effective Vedic multiplication method dependent 4*4 bit arithmetic logic unit having high speed. In this paper, we will perform ALU operations. ALU is a development of research work that has been done for years so we have chosen this topic. Normally ALU is a heart of digital processor, central processing unit, microprocessor and micro controller. Every digital domain based technology has to depend on the performance of ALU. Hence, there is a necessity of ALU which generates high speeds which depends on the speed of multiplier. Therefore, we go for designing a 4-bit multiplier. To generate high speeds, multiplier is employed which is one of the important blocks of the hardware unit and also an important initiation of delay in the path. We have studied many algorithms for multiplication technique but research says that Vedic multiplication is most effective of all in terms of speed. The algorithm contains 16 sutra, out of which we are employing URDHVA TIRYAKBHYAM and the code is written in Very High Speed Integrated Circuit Hardware Description. Our supporting synthesizing and simulating tools are Xilinx ISE9.2i and model sim-altra6.3g-pi (Quartus II) respectively. At last, we will compare 4-bit ALU with 4-bit Array ALU.