Author:
Swathi V,Panduga Kavitha,Kumari Gurrala Shiva
Abstract
Abstract
This article proposes a Vedic multiplier-based design of multiply and accumulate unit by employing UrdhvaTiryagbhyam Sutra. Further, it implements an efficacious ALU with 32-bit architecture. Simulation analysis disclosed the comparison of proposed 32-bit ALU with existing architectures. In addition, complexity in hardware, area and delay reduction demonstrated that proposed 32-bit ALU is more efficient over conventional architectures.
Subject
General Physics and Astronomy
Reference15 articles.
1. Semi-Supervised Recurrent Variational Autoencoder Approach for Visual Diagnosis of Atrial Fibrillation;Costa;IEEE Access,2021
2. An Overview of Human Activity Recognition Using Wearable Sensors: Healthcare and Artificial Intelligence;Liu,2021