1. [1] J. Pak, C. Ryu, and J. Kim, “Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation,” in Proc. IEEE Electromagn. Electron. Mater. Packag., pp. 1-6, November 2007.
2. [2] P.G. Emma and E. Kursun, “ 3D chip technology the next growth engine for performance improvement,” IBM J. Res. Develop., vol. 52, no. 6, pp. 541-552, November 2008.
3. [3] (2013) Technology Roadmap of DRAM for Three Major Manufacturers: Samsung, SK-Hynix and Micron [Online]: Available: http://www.techinsights.com
4. [4] R.R. Tummala, V. Sundaram, R. Chatterjee, P.M. Raj, N. Kumbhat, V. Sukumaran, V. Sridharan, A. Choudury, Q. Chen, and T. Bandyopadhyay, “Trend from ICs to 3D ICs to 3D systems,” in Proc. IEEE Custom Integr. Circuits Conf., San Jose, CA, pp. 439-444, September 2009.
5. [5] M. Sunohara, T. Tokunaga, T. Kurihara, and M. Higashi, “Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring,” in Proc. 58th ECTC, pp. 847-852, May 2008.