Capacitance multiplier with large multiplication factor, high accuracy, and low power and silicon area for floating applications
Author:
Affiliation:
1. Departamento de Electronica, Sistemas e Informatica DESI, Instituto Tecnologico y de Estudios Superiores de Occidente ITESO
2. Instituto Tecnologico de Ciudad Guzman ITCG
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/15/3/15_15.20171191/_pdf
Reference10 articles.
1. [1] I. Padilla-Cantoya and P. M. Furth: “Enhanced grounded capacitor multiplier and its floating implementation for analog filters,” IEEE Trans. Circuits Syst. II, Exp. Briefs 62 (2015) 962 (DOI: 10.1109/TCSII.2015.2435751).
2. [2] F. Matsumotoet al.: “Design of a symmetry-type floating impedance scaling circuits for a fully differential filter,” Analog Integr. Circuits Signal Process. 85 (2015) 253 (DOI: 10.1007/s10470-015-0569-0).
3. [3] J. Aguado-Ruizet al.: “Three novel improved CMOS C-multipliers,” Int. J. Circuit Theory Appl. 40 (2012) 607 (DOI: 10.1002/cta.745).
4. [4] J. Aguado-Ruizet al.: “Programmable capacitance scaling scheme based on operational transconductance amplifiers,” Electron. Lett. 45 (2009) 159 (DOI: 10.1049/el:20093596).
5. [5] J. Choiet al.: “High multiplication factor capacitor multiplier for an on-chip PLL loop filter,” Electron. Lett. 45 (2009) 239 (DOI: 10.1049/el:20092874).
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