A high-throughput network on-chip in full-mesh architecture-Reference-Cited by-同舟云学术

A high-throughput network on-chip in full-mesh architecture

Published:2018 Issue:17 Volume:15 Page:20180635-20180635
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Meng Hongyu¹²,Yang Lei¹,Liu Zijun¹,Wang Donglin¹

Affiliation:

1. Institute of Automation, Chinese Academy of Sciences

2. University of Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/15/17/15_15.20180635/_pdf

Reference14 articles.

1. [1] K. Goossens, et al.: “AEthereal network on chip: Concepts, architectures, and implementations,” IEEE Des. Test Comput. 22 (2005) 414 (DOI: 10.1109/MDT.2005.99).

2. [2] T. Nguyen, et al.: “High-performance adaption of ARM processors into network-on-chip architectures,” IEEE International SOC Conference (2014) 222 (DOI: 10.1109/SOCC.2013.6749691).

3. [3] W. J. Dally and B. Towles: “Route packets, not wires: On-chip interconnection networks,” Proc. 38th Design Automation Conference (2001) 684 (DOI: 10.1109/DAC.2001.156225).

4. [4] B. Grot, et al.: “Express cube topologies for on-chip interconnects,” 2009 IEEE 15th International Symposium on High Performance Computer Architecture (2009) 163 (DOI: 10.1109/HPCA.2009.4798251).

5. [5] G. Chrysos: “Intel^® Xeon Phi coprocessor (codename Knights Corner),” 2012 IEEE Hot Chips 24 Symposium (2012) 1 (DOI: 10.1109/HOTCHIPS.2012.7476487).

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Survey on Network on Chip Routing Algorithms Criteria;Advances on Smart and Soft Computing;2020-10-20