Temperature-dependent characterizations on parasitic capacitance of tapered through silicon via (T-TSV)
Author:
Affiliation:
1. Shaanxi Key Lab. of Integrated Circuits and Systems, School of Microelectronics, Xidian University
2. School of Telecommunications Engineering, Xidian University
3. School of Physics and Optoelectronic, Xidian University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/15/24/15_15.20180878/_pdf
Reference15 articles.
1. [1] F. Wang, et al.: “A novel guard method of through-silicon-via (TSV),” IEICE Electron. Express 15 (2018) 20180421 (DOI: 10.1587/elex.15.20180421).
2. [2] M. Koyanagi: “Recent progress in 3D integration technology,” IEICE Electron. Express 12 (2015) 20152001 (DOI: 10.1587/elex.12.20152001).
3. [3] X. Yin, et al.: “Metal proportion optimization of annular through-silicon via considering temperature and keep-out zone,” IEEE Trans. Compon. Packag. Manuf. Technol. 5 (2015) 1093 (DOI: 10.1109/TCPMT.2015.2446768).
4. [4] Q. Lu, et al.: “Electrical modeling and analysis of Cu-CNT heterogeneous coaxial through-silicon vias,” IEEE Trans. Nanotechnol. 16 (2017) 695 (DOI: 10.1109/TNANO.2017.2708509).
5. [5] X. Liu, et al.: “Electrical modeling and analysis of differential dielectric-cavity through-silicon via array,” IEEE Microw. Wireless Compon. Lett. 27 (2017) 618 (DOI: 10.1109/LMWC.2017.2711563).
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