Area and energy-efficient buffer designs for NoC based on domain-wall memory
Author:
Affiliation:
1. State Key Laboratory of Wide Bandgap Semiconductor Technology Disciplines, Xidian University
2. School of Computer Science & Technology, Xi’an University of Posts & Telecommunications
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Link
https://www.jstage.jst.go.jp/article/elex/18/14/18_18.20210208/_pdf
Reference30 articles.
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2. [2] P.V. Gratz, et al.: “Implementation and evaluation of on-chip network architectures,” 2006 International Conference on Computer Design (ICCD) (2006) 477 (DOI: 10.1109/ICCD.2006.4380859).
3. [3] E.A. Shpiner, et al.: “On the capacity of bufferless networks-on-chip,” IEEE Trans. Parallel Distrib. Syst. 26 (2015) 492 (DOI: 10.1109/TPDS.2014.2310226).
4. [4] E. Morifuji, et al.: “Supply and threshold-voltage trends for scaled logic and SRAM MOSFETs,” IEEE Trans. Electron Devices 53 (2006) 1427 (DOI: 10.1109/TED.2006.874752).
5. [5] Y. Kao and H.J. Chao: “Design of a bufferless photonic clos Network-on-chip architecture,” IEEE Trans. Comput. 63 (2014) 764 (DOI: 10.1109/TC.2012.250).
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