CASSANN-v2: A high-performance CNN accelerator architecture with on-chip memory self-adaptive tuning-Reference-Cited by-同舟云学术

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CASSANN-v2: A high-performance CNN accelerator architecture with on-chip memory self-adaptive tuning

Published:2022-05-25 Issue:10 Volume:19 Page:20220124-20220124
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Liu Feng¹,Qiao Ruixiu²,Chen Gang³,Gong Guoliang¹,Lu Huaxiang⁴

Affiliation:

1. Institute of Semiconductors, Chinese Academy of Sciences

2. Semiconductor Neural Network Intelligent Perception and Computing Technology Beijing Key Laboratory

3. University of Chinese Academy of Sciences

4. Materials and Optoelectronics Research Center, University of Chinese Academy of Sciences

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/19/10/19_19.20220124/_pdf

Reference30 articles.

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2. [2] Z.H. Wu, et al.: “A comprehensive survey on graph neural networks,” IEEE Trans. Neural Netw. Learn. Syst. 32 (2021) C2 (DOI: 10.1109/tnnls.2020.2978386).

3. [3] V. Sze, et al.: “Efficient processing of deep neural networks: a tutorial and survey,” Proc. IEEE 105 (2017) 2295 (DOI: 10.1109/jproc.2017.2761740).

4. [4] M.B. Bejiga, et al.: “A convolutional neural network approach for assisting avalanche search and rescue operations with UAV imagery,” Remote Sensing 9 (2017) 100 (DOI: 10.3390/rs9020100).

5. [5] H.C. Shin, et al.: “Deep convolutional neural networks for computer-aided detection: CNN architectures, dataset characteristics and transfer learning,” IEEE Trans. Med. Imag. 35 (2016) 1285 (DOI: 10.1109/tmi.2016.2528162).

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