A secure SoC architecture design with dual DMA controllers

Abstract

With the continuous advancement of System-on-Chip (SoC) technologies, the burgeoning data volumes emphasize the paramount importance of safeguarding data security and integrity. In this study, by leveraging Ascon in conjunction with enhancements to the SHA-1 algorithm, two secure Direct Memory Access (DMA) controllers are designed to facilitate data encryption and comparison, respectively, culminating in the proposal of an SoC architecture featuring dual DMA controllers. Simulation outcomes demonstrate the system’s ability to achieve a maximum clock frequency of 120 MHz, offering a throughput rate of up to 3.2 GB/s. The multi-master multi-slave AHB bus matrix within the system operates impeccably, ensuring smooth functionality. Furthermore, the two DMA controllers exhibit independent operation, featuring flexible start-stop capabilities. Notably, they operate harmoniously without conflicts, optimizing the area utilization while adhering to a low power consumption design methodology. The results unequivocally affirm the feasibility of designing a secure SoC integrated with two DMA controllers. This hardware-based approach effectively ensures data security, showcasing promising prospects for real-world applications.