Energy-efficient Fe-based FET logic in LUT circuit with transistor reduction technique-Reference-Cited by-同舟云学术

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Energy-efficient Fe-based FET logic in LUT circuit with transistor reduction technique

Published:2022-03-25 Issue:6 Volume:19 Page:20220004-20220004
ISSN:1349-2543
Container-title:IEICE Electronics Express
language:en
Short-container-title:IEICE Electron. Express

Author:

Chen Zhijie¹,Zhang Yu¹,Gao Zhiyuan¹,Wan Peiyuan¹

Affiliation:

1. Faculty of Information Technology, Beijing University of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/elex/19/6/19_19.20220004/_pdf

Reference30 articles.

1. [1] J. Müller, et al.: “Ferroelectric hafnium oxide: a CMOS-compatible and highly scalable approach to future ferroelectric memories,” IEEE International Electron Devices Meeting (IEDM) Tech. Dig. (2013) 10.8.1 (DOI: 10.1109/iedm.2013.6724605).

2. [2] A. Chen: “Emerging nonvolatile memory (NVM) technologies,” 2015 45th European Solid State Device Research Conference (ESSDERC) (2015) 109 (DOI: 10.1109/essderc.2015.7324725).

3. [3] M. Pesic, et al.: “Reliability aspects of novel anti-ferroelectric non-volatile memories compared to hafnia based ferroelectric memories,” IEEE International Integrated Reliability Workshop (IIRW) 2017 (2017) 1 (DOI: 10.1109/iirw.2017.8361237).

4. [4] K.-T. Chen, et al.: “Non-volatile ferroelectric FETs using 5-nm Hf0.5Zr0.5O2 with high data retention and read endurance for 1T memory applications,” IEEE Electron Device Lett. 40 (2019) 399 (DOI: 10.1109/led.2019.2896231).

5. [5] Z. Wang, et al., “Experimental demonstration of ferroelectric spiking neurons for unsupervised clustering,” 2018 IEEE International Electron Devices Meeting (IEDM) (2018) 13.3.1 (DOI: 10.1109/IEDM.2018.8614586).

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